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Espressif Systems /ESP32-S2 /TIMG0 /WDTCONFIG0

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Interpret as WDTCONFIG0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (WDT_APPCPU_RESET_EN)WDT_APPCPU_RESET_EN 0 (WDT_PROCPU_RESET_EN)WDT_PROCPU_RESET_EN 0 (WDT_FLASHBOOT_MOD_EN)WDT_FLASHBOOT_MOD_EN 0WDT_SYS_RESET_LENGTH 0WDT_CPU_RESET_LENGTH 0 (WDT_LEVEL_INT_EN)WDT_LEVEL_INT_EN 0 (WDT_EDGE_INT_EN)WDT_EDGE_INT_EN 0WDT_STG3 0WDT_STG2 0WDT_STG1 0WDT_STG0 0 (WDT_EN)WDT_EN

Description

Watchdog timer configuration register

Fields

WDT_APPCPU_RESET_EN

Reserved.
WDT_PROCPU_RESET_EN

WDT reset CPU enable.
WDT_FLASHBOOT_MOD_EN

When set, Flash boot protection is enabled.
WDT_SYS_RESET_LENGTH

System reset signal length selection. 0: 100 ns. 1: 200 ns. 2: 300 ns. 3: 400 ns. 4: 500 ns. 5: 800 ns. 6: 1.6 us. 7: 3.2 us.
WDT_CPU_RESET_LENGTH

CPU reset signal length selection. 0: 100 ns. 1: 200 ns. 2: 300 ns. 3: 400 ns. 4: 500 ns. 5: 800 ns. 6: 1.6 us. 7: 3.2 us.
WDT_LEVEL_INT_EN

When set, a level type interrupt will occur at the timeout of a stage configured to generate an interrupt.
WDT_EDGE_INT_EN

When set, an edge type interrupt will occur at the timeout of a stage configured to generate an interrupt.
WDT_STG3

Stage 3 configuration. 0: off. 1: interrupt. 2: reset CPU. 3: reset system.
WDT_STG2

Stage 2 configuration. 0: off. 1: interrupt. 2: reset CPU. 3: reset system.
WDT_STG1

Stage 1 configuration. 0: off. 1: interrupt. 2: reset CPU. 3: reset system.
WDT_STG0

Stage 0 configuration. 0: off. 1: interrupt. 2: reset CPU. 3: reset system.
WDT_EN

When set, MWDT is enabled.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data